(1) Field of the Invention
The present invention relates to a variable-length code decoding apparatus and a method for decoding a bitstream containing codewords that are variable-length encoded data.
(2) Description of the Related Art
Recent years have seen marked development in compression encoding techniques for moving pictures, audio, and so on, and such techniques are being practically applied in fields such as broadcasting, communications, and storage. Variable-length encoding is a compression encoding technique that improves encoding efficiency by varying the code length based on the frequency at which values to be encoded arise. When decoding variable-length encoded data (denoted as “codewords” hereinafter), the code lengths of the codewords contained in a bitstream differ from each other, and thus it is not possible to identify the location of a given codeword. It is thus necessary to sequentially decode the codewords starting with the beginning of the bitstream. Meanwhile, with standards such as MPEG (Moving Picture Experts Group), predetermined units for decoding are specified, and a DTS (Decoding Time Stamp) is held in the header of each unit for decoding.
A variable-length code decoding apparatus disclosed in, for example, Japanese Unexamined Patent Application Publication No. H11-122113 (hereinafter referred to as Patent Reference 1) is known as a variable-length code decoding apparatus that decodes variable-length encoded codewords.
FIG. 16 is a diagram illustrating the configuration of the conventional variable-length code decoding apparatus disclosed in Patent Reference 1. The variable-length code decoding apparatus illustrated in FIG. 16 includes a video decoder 600 and a memory 700.
The video decoder 600 decodes code data of images (a bitstream) compression-encoded through an MPEG technique. The video decoder 600 includes an input interface 610, a memory interface 620, an image decompression unit 630, an output interface 640, and a controller 650.
The image decompression unit 630, meanwhile, includes a VLD (Variable Length Decoding) unit 631, an IQ (Inverse Quantization) unit 632, an IDCT (Inverse Discrete Cosine Transform) unit 633, an MVC (Motion Vector Calculation) unit 634, an MC (Motion Compensation) unit 635, a byte-word conversion unit 636, a clock control unit 637, and a parser unit 638.
The memory 700 includes a code buffer memory 710 and a frame memory 720. The code buffer memory 710 accumulates an undecoded bitstream.
The byte-word conversion unit 636 converts the undecoded bitstream accumulated in the code buffer memory 710 from byte units to word units and outputs the word units. The byte-word conversion unit 636 also outputs an underflow signal to the clock control unit 637 until a predetermined amount of the undecoded bitstream has been accumulated in the code buffer memory 710.
The clock control unit 637 does not supply a clock signal to the VLD unit 631 during the period in which the underflow signal is being outputted by the byte-word conversion unit 636.
The VLD unit 631 decodes the undecoded bitstream outputted by the byte-word conversion unit 636 using a variable-length code table during the period in which the clock signal is being supplied by the clock control unit 637.
Through the configuration described thus far, when decoding a predetermined unit for decoding, the conventional variable-length code decoding apparatus illustrated in FIG. 16 can commence the decoding at the point in time when the predetermined amount of the undecoded bitstream has been accumulated rather than waiting until a decoding start time, which makes it possible to use hardware resources in an efficient manner.
However, the aforementioned conventional variable-length code decoding apparatus has been problematic in that although the decoding can be commenced at the point in time when the predetermined amount of the undecoded bitstream has been accumulated, the decoding cannot be completed in the case where the code length of the codeword at the end of the bitstream is less than a predetermined amount.
As a result, the aforementioned conventional variable-length code decoding apparatus cannot execute decoding of the entire bitstream, and in the case where, for example, the bitstream is a moving picture, there are problems where the final picture cannot be outputted and so on. For this reason, the technique disclosed in Patent Reference 1 is, for example, applied only to the first picture, whereas normal decoding based on DTSs is executed on the pictures that follow thereafter. In other words, the conventional variable-length code decoding apparatus has not been able to be applied from the start to the end of a bitstream.
The present invention solves the aforementioned conventional problems, and it is an object thereof to provide a variable-length code decoding apparatus capable of commencing decoding at the point in time when a predetermined amount of an undecoded bitstream has been accumulated and capable of completing decoding even in the case where the code length of the codeword at the end of a bitstream is less than a predetermined amount. Through this, decoding of a bitstream can be executed prior to DTS, and decoding can be executed on the entire bitstream.